In many applications, it is desirable to sample signals at a rate that is higher than possible using a single analog-to-digital converter (ADC). In such applications, multiple (“N”) ADCs may be employed and operated at 1/Nth of the desired sampling rate. Also, a timing offset is applied between the sampling of each ADC which ideally is the desired sampling period TS. The operation of multiple ADCs in this manner approximates the operation of a single ADC operating at the higher sampling rate. This method is commonly referred to as interleaved sampling. A similar technique can be applied to digital-to-analog converters (DACs) where multiple slower DACs are concatenated to effect a single higher speed DAC.
In practice, errors exist in the timing offsets between sampling by the discrete ADCs. Specifically, the time between sampling from adjacent ADCs differs slightly from the desired sampling period TS. Also, the gain of the multiple ADCs typically varies slightly. The timing errors and the gain errors degrade the reconstructed output signal. Because the timing errors and gain errors are associated with specific discrete ADCs, the timing and gain errors are periodic with a period of N samples. Similar time and gain errors are typically experienced by concatenated DACs.
Known interleaved sampling devices employ analog trims. The analog trims are used to apply a delay and/or loss of a predetermined amount to the signal before sampling by a respective ADC to compensate for timing and/or gain errors.